1. Technical Field
This invention relates to the manufacture of advanced semiconductor devices, and more particularly, to a method related to formation of a gate electrode that employs a conductive hard mask as a protective layer during a photoresist removal process for multiple work function gate structures.
2. Related Art
The ongoing reduction in size of electronic device elements poses problems in device performance that must be addressed using new materials and fabrication techniques. In the case of gate structures for high-performance complementary metal-oxide semiconductor (CMOS) devices, the equivalent oxide thickness of the gate dielectric has been reduced to about 1.2 nm. A typical CMOS gate structure is shown schematically in FIG. 1. Gate structure 10 is fabricated on the surface of a substrate 12, which has source and drain regions 14, 16 formed therein. Gate structure 10 includes conducting element 18 (typically polysilicon; p+ doped and n+ doped in PFETs and NFETs, respectively) overlying dielectric layer 20. If a conventional oxynitride gate dielectric is used, decreasing the thickness below about 1.2 nm (physical thickness of the dielectric) causes the gate leakage current to become unacceptably high. In a structure such as shown in FIG. 1, the total gate electrical thickness may be viewed as having three components: the equivalent oxide thickness of the gate dielectric (about 1.2 nm), the quantum-mechanical effect of the substrate (about 0.4 nm), and the polysilicon depletion effect (about 0.3 to 0.4 nm). With present-day gate dielectric thicknesses, the polysilicon depletion effect accounts for a substantial component of the total gate electrical thickness. The polysilicon depletion effect comes about when the gate is turned on and a region devoid of free charge forms at the polysilicon/dielectric interface (interface 20A in FIG. 1). The appearance of this depletion region reduces the capacitance of the gate and thus increases the electrical thickness. If the polysilicon depletion region could be eliminated, the electrical dielectric thickness would be reduced with no substantial increase in the leakage current. This would permit improved device performance without a further reduction in the thickness of the gate dielectric 12.
Linewidths are also being reduced to less than 65 nm. In the case of CMOS, this means that the lateral extent of gate structure 10 is now in the sub-65 nm range. If a gate structure about this size is designed with a gate dielectric equivalent thickness of about 1 nm, a conventional oxynitride gate dielectric can no longer be used due to unacceptably high leakage currents. It then becomes necessary to substitute high-k gate dielectric materials for the conventional gate oxide or oxynitride, which serves to lower the gate leakage current by 4 to 5 orders of magnitude while having similar equivalent oxide thickness. However, the combination of polysilicon for gate conductor 18 with a high-k material for gate dielectric 20 presents further problems. As is understood by those skilled in the art, interactions between the materials can cause a shift in the threshold voltage Vt due to pinning of the Fermi level in the gate conductor. In particular, an increased Vt may prevent proper function in a PFET. Another problem affecting PFET performance is that of penetration of boron from the p+ type polysilicon into the high-k dielectric and possibly into the channel region of the device, which renders the device unusable. In addition, the boron diffusion also interferes with hafnium containing high-k dielectrics.
Accordingly, in a PFET device (at least) it is desirable to eliminate the polysilicon from the gate structure (or at least remove the polysilicon from contact with the gate dielectric), as several benefits may be obtained. The elimination of the polysilicon depletion effect would decrease the effective electrical thickness of the gate dielectric. Interactions between the polysilicon and gate dielectric materials would be avoided, which in turn would avoid the problem of boron penetration. This would lead to faster devices that consume less power.
Recently there has been substantial interest in replacing polysilicon gate conductors with metal gate electrodes, so that gate conductor 18 is a metal in both NFET and PFET devices. In order to provide appropriate threshold voltages in the two types of devices, two different metals are typically needed. In addition, the NFET and PFET require metals with different work functions. The “work function” of a material is a measurement of how much energy is required to extract an electron from the material by moving the electron in the solid from the Fermi level to the vacuum level, i.e., to outside of the solid. Generally, an NFET device should have a gate work function in the range 4.1 to 4.3 eV, and a PFET device should have a gate work function over 5.0 eV. Furthermore, the interface 12A between the metal and the gate dielectric should be stable during the high-temperature processing steps in the fabrication of the CMOS devices.
There are two possible integration approaches for metal gate conductors in CMOS; these are referred to as the conventional processing approach and the replacement gate approach. In the conventional processing approach, the metal is in contact with the gate dielectric during the high-temperature (above 1000° C.) activation annealing steps for the dopants in the source and drain regions. The metal must not interact with the dielectric material during the annealing steps. In the replacement gate approach, the CMOS structure is first formed with polysilicon gate electrodes. After all of the high-temperature processing steps, the polysilicon and gate dielectric are removed and a new dielectric is formed, followed by deposition of the metal gate conductor. With this approach the metal/dielectric interface needs to be stable only up to about 500° C. In either process flow, in order to create two gate materials with different work functions, one has to selectively remove the first gate material from the area designated for the second material. This selective removal can be easily accomplished with the aid of standard photolithography techniques where the first material is selectively protected by a photoresist mask in the first area and is selectively removed in the second area. After selective gate material removal, the photoresist mask is stripped. Unfortunately, current technology implements such a photoresist strip with the aid of an oxidizing ambient (e.g. oxygen or ozone plasma) and/or an oxidizing chemical solution (e.g. a solution of sulfuric acid (H2SO4) with oxidizing peroxide H2O2). Presence of oxidizers (dry or wet) can substantially thicken the exposed gate dielectric which leads to a substantial degradation of performance. The absence of oxidizing agents in the resist strip can lead to a defective layer formation in the gate dielectric and the gate electrode. For example, the non-oxidizing solvent resist strip can create impurity contamination like carbon on a gate oxide and incomplete uniform resist strip. In addition, typical metal gate electrode materials (e.g., tungsten nitride (WNx), titanium nitride (TiN), hafnium nitride (HfN) or zirconium nitride (ZN)) can be easily etched out by chemicals such as a mixture of sulfuric acid (H2SO4) and/or peroxide (H2O2) during photoresist strip. Accordingly, the first gate material can be also damaged during a typical photoresist strip process.
In view of the foregoing, there is a need in the art for a method that does not suffer from the problems of the related art.